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flash memory 1 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d k9xxg08uxd * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 2 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d document title 4g x 8 bit/ 8g x 8 bit/ 16g x 8 bit nand flash memory revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung elec tronics will evaluate and reply to your requests and questions about device. if you h ave any questions, please contact the samsung branch office near your office. revision no 0.0 0.1 0.2 remark advance preliminary history 1. initial issue 1. k9pdg08u5d-l?s package thickness is changed. 2. ce and r/b pin location of k9pdg08u5d-l is changed. 1. interleaving operation is modified. 2. interleaving page read operation is added. draft date mar. 14th 2008 oct. 16th 2008 www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 3 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d 4g x 8 bit/ 8g x 8 bit/ 16g x 8 bit nand flash memory product list part number vcc range organization pkg type K9LBG08U0D-p 2.7v ~ 3.6v x8 tsop1 k9hcg08u1d-p k9mdg08u5d-p tsop1-dsp k9hcg08u1d-i 52tlga k9pdg08u5d-l 52tlga(14x18) general description features ? voltage supply - 3.3v device : 2.7v ~ 3.6v ? organization - memory cell array : (2g + 109m) x 8bit - data register : (4k + 218) x 8bit ? automatic program and erase - page program : (4k + 218)byte - block erase : (512k + 27.25k)byte ? page read operation - page size : (4k + 218)byte - random read : 60 s(max.) - serial access : 30ns(min.) *k9xdg08u5d: 50ns(min.) ? memory cell : 2bit / memory cell ? fast write cycle time - program time : 800 s(typ.) - block erase time : 1.5ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology - endurance : tbd cycles(with tbd ecc) - data retention : tbd years ? command register operation ? unique id for copyright protection ? package : - K9LBG08U0D-pcb0/pib0 : pb-free package 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - k9hcg08u1d-pcb0/pib0 : pb-free package 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - k9mdg08u5d-pcb0/pib0: two k9hcg08u1d packages stacked 48 - pin tsop i (12 x 20 / 0.5 mm pitch) : pb-free package - k9hcg08u1d-icb0/iib0 52 - pin tlga (12 x 17 / 1.00 mm pitch) - k9pdg08u5d-lcb0/lib0 : pb/halogen-free package 52 - pin tlga (14 x 18 / 1.00 mm pitch) offered in 4gx8bit, the K9LBG08U0D is a 32g -bit nand flash memory with spare 1,744m -bit. the device is offered in 3.3v vcc . its nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation can be perform ed in typical 800 s on the 4,314-byte page and an erase operation can be performed in typical 1.5ms on a (512k+27.25k)byte block. data in the data register can be read out at 30ns(k9xdg08u5d: 50ns) cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. the on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verifica tion and margining of data. even the write-intensive systems c an take advantage of the K9LBG08U0D s extended reliability of tbd cycl es by providing ecc(error correc ting code) with real time map- ping-out algorithm. the K9LBG08U0D is an optimum solution for la rge nonvolatile storage applications such as solid state file s tor- age and other portable applicati ons requiring non-volatility. www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 4 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d pin configuration (tsop1) K9LBG08U0D-pcb0/pib0 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c n.c package dimensions 48-pin lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220af unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.16 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 0.20 +0.07 -0.03 www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 5 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d pin configuration (tsop1) 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c r/b2 r/b1 re ce1 ce2 n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220af unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.16 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.02 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 0.20 +0.07 -0.03 k9hcg08u1d-pcb0/pib0 www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 6 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d 18.80 max ref 12.40 max ref 0.13~0.23 pin #1 #1 #24 #48 0.50 typ #25 (0.10) a (0.249) basic gage plane 0.399~0.600 20.00 0.20 0.02 min 2.35 max typ both sides bottom tsop only (0.10) a -a- seating pin configuration (tsop1-dsp) package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220af unit :mm/inch plane 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-pin tsop1 dual stacked package 12mm x 20mm n.c n.c n.c r/b2 r/b1 re ce1 ce2 n.c vcc vss cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c n.c r/b4 r/b3 ce3 ce4 k9mdg08u5d-pcb0/pib0 www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 7 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d 1.00 1.00 1.00 1.00 2.00 7 6 5 4 3 2 1 1.00 1.00 1.00 12.00 0.10 #a1 17.00 0.10 17.00 0.10 b a 12.00 0.10 (datum b) (datum a) 12.0 0 10.00 2.50 2.50 2.00 0.50 1.30 a b c d e f g h j k l m n 12- ? 1.00 0.05 41- ? 0.70 0.05 side view 1.0 ( max .) 0.10 c 17.00 0.10 top view bottom view ab c d e f g h j k l m n 7 6 5 4 3 2 1 k9hcg08u1d - icb0 / iib0 52-tlga (measured in millimeters) nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc vcc vcc vss vss vss /re1 /re2 /ce1 /ce2 cle1 cle2 ale1 ale2 /we1 /we2 /wp1 /wp2 r/b1 r/b2 vss io0-1 io0-2 io1-1 io1-2 io2-1 io3-1 io2-2 io3-2 io4-1 io4-2 io5-1 io5-2 io6-1 io6-2 io7-1 io7-2 ? ab c m 0.1 ? ab c m 0.1 package dimensions pin configuration (tlga) www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 8 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d ab c d e f g h j k l m n 7 6 5 4 3 2 1 k9pdg08u5d-lcb0/lib0 1.00 1.00 1.00 1.00 2.00 7 6 5 4 3 2 1 1.00 1.00 1.00 14.00 0.10 #a1 18.00 0.10 18.00 0.10 b a 14.00 0.10 (datum b) (datum a) 12.0 0 10.00 2.50 2.50 2.00 0.50 1.30 a b c d e f g h j k l m n 12- ? 1.00 0.05 41- ? 0.70 0.05 side view 0.10 c 18.00 0.10 top view bottom view 52-tlga (measured in millimeters) ? ab c m 0.1 ? ab c m 0.1 package dimensions 1.0 ( max .) nc nc nc nc nc nc nc nc nc vcc vcc /ce2-1 r/b2-1 vcc vcc vss vss vss /re1 /re2 /ce1-1 /ce1-2 cle1 cle2 ale1 ale2 /we1 /we2 wp1 /wp2 r/b1-1 r/b1-2 vss io0-1 io0-2 io1-1 io1-2 io2-1 io3-1 io2-2 io3-2 io4-1 io4-2 io5-1 io5-2 io6-1 io6-2 io7-1 io7-2 vss r/b2-2 /ce2-2 www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 9 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. there are two ce pins (ce 1 & ce 2 ) in the k9hcg08u1d, and four ce pins (ce 1 & ce 2 & ce 3 & ce 4 ) in the k9xdg08u5d. there are two r/b pins (r/b 1 & r/b 2 ) in the k9hcg08u1d, and four r/b pins (r/b 1 & r/b 2 & r/b 3 & r/b 4 ) in the k9xdg08u5d. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and dat a, and to output data during read operations. the i/ o pins float to high-z when the chip is des elected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for comm ands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for addres s to the internal address registers. addresses are latched on the rising edge of we with ale high. ce / ce1 chip enable the ce / ce 1 input is the device selection control. when the device is in the busy state, ce / ce1 high is ignored, and the device does not return to standby mode in program or erase operation. regarding ce / ce 1 control during read operation , refer to ?page read? section of device operation ce2 chip enable the ce 2 input enables the second K9LBG08U0D re read enable the re input is the serial data-out control, and when active drives the data onto t he i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands , address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent program/erase protecti on during power transitions. the internal high volt- age generator is reset when the wp pin is active low. r/b / r/b 1 ready/busy output the r/b / r/b 1 output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and retu rns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. r/b 2 ready/busy output the r/b 2 output indicates the status of the second K9LBG08U0D. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 10 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d 4k bytes 218 bytes figure 1. K9LBG08U0D functional block diagram figure 2. K9LBG08U0D array organization v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 13 - a 32 a 0 - a 12 command ce re we cle wp i/0 0 i/0 7 v cc v ss 1,024k pages (=8,192 blocks) 4k bytes 8 bit 218 bytes 1 block = 128 pages (512k + 27.25k) bytes i/o 0 ~ i/o 7 1 page = (4k + 218)bytes 1 block = (4k + 218)b x 128 pages = (512k +27.25k) bytes 1 device = (4k + 218)b x 128 pages x 8,192 blocks = 34,512 mbits page register ale 32,768m + 1,774m bit nand flash array (4,096 + 218)byte x 1,048,576 y-gating data register & s/a note : column address : starting address of the register. * l must be set to ?low?. * the device ignores any additional i nput of address cycles than required. * row address consis ts of page address (a 13 ~ a 19 ) & plane address(a 20 ) & block address(a 21 ~ the last address) i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 a 12 *l *l *l 3rd cycle a 13 a 14 a 15 a 16 a 17 a 18 a 19 a 20 4th cycle a 21 a 22 a 23 a 24 a 25 a 26 a 27 a 28 5th cycle a 29 a 30 a 31 a 32 *l *l *l *l row address; column address plane address : a 20 block address : a 21 ~ the last address page address : a 13 ~ a 19 www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 11 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d product introduction nand flash memory has addresses multiplexed into 8 i/os. this scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in sy stem board design. command, address and data are all written throu gh i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address re spectively, via the i/o pins. some commands require one bus cycle. for example, reset command, status read command, etc. require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution.. page read and page program need the same five address cycles following the required command input. in bl ock erase operation, however, only the thr ee row address cycles are used. device operations are selected by writing specific commands into the command register. table 1 defines the specific commands of the K9LBG08U0D. table 1. command sets note : 1. random data input/output can be executed in a page. 2. any command between 11h and 80h/81h/85h is prohibited except 70h/f1h/f2h and ffh. 3. two-plane random data out must be used after two-plane read or two-plane cache read operation 4. interleave-operation between two chips is allowed. caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st set 2nd set read 00h 30h read for copy back 00h 35h cache read 31h - read start for last page cache read 3fh - page program 80h 10h cache program 80h 15h copy-back program 85h 10h block erase 60h d0h random data input (1) 85h - random data output (1) 05h e0h two-plane read (3) 60h----60h 30h two-plane read for copy-back (3) 60h----60h 35h two-plane random data output (1) (3) 00h----05h e0h two-plane cache read (3) 60h----60h 33h two-plane page program (2) 80h----11h 81h----10h two-plane copy-back program (2) 85h----11h 81h----10h two-plane cache program (2) 80h----11h 81h----15h two-plane block erase 60h----60h d0h read id 90h - read status 70h - o chip1 status f1h o chip2 status f2h o reset ffh - o www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 12 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d K9LBG08U0D is arranged in four 8gb memory planes. each plane contains 2,048 blocks and 4314 byte page registers. this allows it to perform simultaneous page program and block erase by select ing one page or block from each plane. the block address map is configured so that two-plane program/erase operations can be exec uted by dividing the memory array into plane 0~1 or plane 2~3 separately. for example, two-plane program/erase operation into plane 0 and plan e 2 is prohibited. that is to say, two-plane program/erase oper- ation into plane 0 and plane 1 or into plane 2 and plane 3 is allowed. memory map plane 0 plane 1 plane 2 plane 3 (2048 block) (2048 block) (2048 block) (2048 block) page 0 page 1 page 127 page 126 block 0 page 0 page 1 block 1 page 0 page 1 block 4096 page 0 page 1 block 4097 page 0 page 1 block 4094 page 0 page 1 block 4095 page 0 page 1 block 8190 page 0 page 1 block 8191 4314byte page registers 4314byte page registers 4314byte page registers 4314byte page registers page 0 page 1 block 2 page 0 page 1 block 3 page 0 page 1 block 4098 page 0 page 1 block 4099 page 0 page 1 block 4092 page 0 page 1 block 4093 page 0 page 1 block 8188 page 0 page 1 block 8189 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 page 127 page 126 www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 13 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d recommended operating conditions (voltage reference to gnd, k9xxg08uxd-xcb0 : t a =0 to 70 c, k9xxg08uxd-xib0 : t a =-40 to 85 c) parameter symbol min typ. max unit supply voltage v cc 2.7 3.3 3.6 v supply voltage v ss 000v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during trans itions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet . exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v cc -0.6 to + 4.6 v v in -0.6 to + 4.6 v i/o -0.6 to vcc+0.3 (<4.6v) temperature under bias k9xxg08uxd-xcb0 t bias -10 to +125 c k9xxg08uxd-xib0 -40 to +125 storage temperature k9xxg08uxd-xcb0 t stg -65 to +150 c k9xxg08uxd-xib0 short circuit current ios 5 ma dc and operating characteristics (recommended operating cond itions otherwise noted.) note : 1. v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. 2. typical value is measured at vcc=3.3v, t a =25 c. not 100% tested. 3. the typical value of the k9hcg08u1d?s i sb 2 is 40 a and the maximum value is 200 a. 4. the typical value of the k9xdg08u5d?s i sb 2 is 80 a and the maximum value is 400 a. 5. the maximum value of k9hcg08u1d-p?s i li and i lo is 40 a. 6. the maximum value of k9pdg08u5d-l?s i li and i lo is 40 a and k9mdg08u5d-p?s i li and i lo is 80 a. parameter symbol test conditions min typ max unit operating current page read with serial access i cc 1 trc=30ns (k9xdg08u5d: 50ns) ce =v il, i out =0ma -1535 ma program i cc 2- erase i cc 3- stand-by current(ttl) i sb 1ce =v ih , wp =0v/v cc --1 stand-by current(cmos) i sb 2ce =v cc -0.2, wp =0v/v cc - 20 100 a input leakage current i li v in =0 to vcc(max) - - 20 output leakage current i lo v out =0 to vcc(max) - - 20 input high voltage v ih (1) - 0.8 xvcc - vcc +0.3 v input low voltage, all inputs v il (1) - -0.3 - 0.2 xvcc output high voltage level v oh i oh =-400 a2.4-- output low voltage level v ol i ol =2.1ma - - 0.4 output low current(r/b )i ol (r/b )v ol =0.4v 8 10 - ma www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 14 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d valid block note : 1. the device may include initial invalid blocks when first shipped. additional invalid blocks may develop while being used. th e number of valid blocks is presented with both cases of invalid blocks considered. invalid bl ocks are defined as blocks that contain one or more bad bits which cause status fail- ure during program and erase operation. do not erase or program factory-marked bad blocks. refer to the attached technical note s for appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment 3. the number of valid blocks is on the basis of single pl ane operations, and this may be de creased with two plane operations. * : each K9LBG08U0D chip in the k9hcg08u1d, k9xdg08u5d has maximum 200 invalid blocks. parameter symbol min typ. max unit K9LBG08U0D n vb 7,992 - 8,192 blocks k9hcg08u1d 15,984 - 16,384 k9xdg08u5d 31,968 - 32,768 mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode hll hx read mode command input l h l h x address input(5clock) hll hh write mode command input l h l h h address input(5clock) l l l h h data input lllh x data output x x x x h x during read(busy) xxxxxh during program(busy) xxxxxh during erase(busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by capacitance ( t a =25 c, v cc =3.3v, f=1.0mhz) note : 1. capacitance is periodically sampled and not 100% tested. 2. c i/o(w) and c in(w) are tested at wafer level. 3. k9hcg08u1d-ixb0?s capacitance(i/o, inpu t) is 13pf and k9pdg08u5d-lxb0?s ca pacitance(i/o, input) is 23pf. item symbol test condition K9LBG08U0D k9hcg08u1d k9mdg08u5d unit min max min max min max input/output capacitance c i/o v il =0v -13-23-43pf c i/o(w)* -10-20-40pf input capacitance c in v in =0v -13-23-43pf c in(w)* -10-20-40pf ac test condition (k9xxg08uxd-xcb0 :t a =0 to 70 c, k9xxg08uxd-xib0:t a =-40 to 85 c, k9xxg08uxd: vcc=2.7v ~ 3.6v,unless otherwise noted) parameter k9xxg08uxd input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load 1 ttl gate and cl=50pf (K9LBG08U0D-p, k9hcg08u1d-i) 1 ttl gate and cl=30pf (k9hcg08u1d-p, k9xdg08u5d-p/l) www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 15 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d program / erase characteristics note : 1. typical program time is measured at vcc=3.3v, ta=25 c. not 100% tested. 2. typical program time is defined as the time within which more than 50% of the whole pages are programed at 3.3v v cc and 25 c temperature. 3. within a same block, program time(tprog) of page group a is faster than that of page group b. typical tprog is t he average program time of the page group a and b(table 5). page group a: page 0, 1, 2, 3, 6, 7, 10, 11, ... , 110, 111, 114, 115, 118, 119, 122, 123 page group b: page 4, 5, 8, 9, 12, 13, 16, 17, ... , 116, 117, 120, 121, 124, 125, 126, 127 4. t cbsy depends on the timing between internal programming time and data in time. parameter symbol min typ max unit program time t prog -0.83 ms dummy busy time for two-plane program t dbsy -0.51 s dummy busy time for cache program t cbsy --3ms number of partial program cycles in the same page nop - - 1 cycle block erase time t bers -1.510ms ac timing characteristics for command / address / data input notes : 1. the transition of the corresponding cont rol pins must occur only once while we is held low 2. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle parameter symbol min max unit K9LBG08U0D k9xdg08u5d K9LBG08U0D k9xdg08u5d k9hcg08u1d k9hcg08u1d cle setup time t cls (1) 15 25 - - ns cle hold time t clh 510- -ns ce setup time t cs (1) 20 35 - - ns ce hold time t ch 510- -ns we pulse width t wp 15 25 - - ns ale setup time t als (1) 15 25 - - ns ale hold time t alh 510- -ns data setup time t ds (1) 15 20 - - ns data hold time t dh 510- -ns write cycle time t wc 30 45 - - ns we high hold time t wh 10 15 - - ns address to data loading time t adl (2) 100 100 - - ns www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 16 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5 s. parameter symbol min max unit K9LBG08U0D k9xdg08u5d K9LBG08U0D k9xdg08u5d k9hcg08u1d k9hcg08u1d data transfer from cell to register t r -6060 s ale to re delay t ar 10 10 - ns cle to re delay t clr 10 10 - ns ready to re low t rr 20 20 - ns re pulse width t rp 15 25 - ns we high to busy t wb - - 100 100 ns wp high to we low t ww 100 100 ns read cycle time t rc 30 50 - ns re access time t rea - - 20 30 ns ce access time t cea - - 25 45 ns re high to output hi-z t rhz - - 100 100 ns ce high to output hi-z t chz - - 30 30 ns ce high to ale or cle don?t care t csd 00- ns re high to output hold t rhoh 15 15 - ns re low to output hold t rloh 5-- ns re high hold time t reh 10 15 - ns output hi-z to re low t ir 00- ns re high to we low t rhw 100 100 - ns we high to re low t whr 60 60 - ns device resetting time(read/pro- gram/erase) t rst -- 5/10/500 (1) 5/10/500 (1) s cache busy in read cache (following 31h and 3fh) t dcbsyr - - 65 65 s www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 17 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d nand flash technical notes initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial inva lid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is called the initial invalid block inform ation. devices with initial in valid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid bl ock(s) does not affect the performance of valid bl ock(s) because it is isolated from the bi t line and the common source line by a sele ct tran- sistor. the system design must be able to mask out the initial in valid block(s) via address mappi ng. the 1st block, which is pl aced on 00h block address, is guaranteed to be a valid block at the time of shipment. identifying initial invalid block(s) all device locations are erased(ffh) except locations where the initial invalid block(s) information is written prior to shippi ng. the initial invalid block(s) status is defined by the 1st byte in the spare area. samsung makes sure that the last page of every in itial invalid block has non-ffh data at the column address of 4,096.the initial invalid block information is al so erasable in most cases, and it is impossible to recover the information once it has been erased. t herefore, the system must be able to recognize the initial inva lid block(s) based on the initial invalid bl ock information and create the initial inva lid block table via the following suggested flow chart(figure 3). any intentional erasure of the initial invalid block information is prohibited. * check "ffh" at the column address figure 3. flow chart to create initial invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no initial invalid block(s) table 4,096 of the last page in the block www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 18 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes error in write or read operation within its life time, additional invalid bl ocks may develop with nand flash memory. refer to the qualification report for the a ctual data. block replacement should be done upon erase or program error. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read up to eight bit failur e verify ecc -> ecc correction ecc : error correcting code --> rs code or bch code etc. example) 8bit correction / 512-byte : if program operation results in an error, map out the block including the page in error and copy the * target data to another block. www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 19 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) write 30h block replacement * step1 when an error happens in the nth page of the bloc k ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program block ?a? by creating an ?i nvalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2 www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 20 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d within a block, the pages must be programmed consecutively from the lsb (least significant bit) page of the block to msb (most sig- nificant bit) pages of the block. random page address programming is prohibited. in this case, the definition of lsb page is th e lsb among the pages to be programmed. therefore, lsb doesn?t need to be page 0. from the lsb page to msb page data in: data (1) data (128) (1) (2) (3) (32) (128) data register page 0 page 1 page 2 page 31 page 127 ex.) random page program (prohibition) data in: data (1) data (128) (2) (32) (3) (1) (128) data register page 0 page 1 page 2 page 31 page 127 addressing for program operation : : : : interleaving operation ddp device is composed of two chips s haring ce pin. ddp device provides interleaving operation between two chips this interleaving operation improves the system throughput almost twice co mpared to non-interleaving operation. at first, the host issues a operation command to one of the lsb ch ips, say (chip #1). due to ddp device goes into busy state. d uring this time, msb chip (chip #2) is in ready state. so it can execute the operation command issued by the host. after the execution of operation by lsb ch ip (chip #1), it can execute another operat ion regardless of msb chip (chip #2). bef ore that the host needs to check the status of lsb chip (chip #1) by issuing f1h command. only when the status of lsb chip (chip #1) becomes ready status, host can issue another operation command. if l sb chip (chip #1) is in busy state, the host has to wait fo r lsb chip (chip #1) to get into ready state. similarly, msb chip (chip #2) can execut e another operation after the completion of the previous operation. the host can monit or the status of msb chip (chip #2) by issuing f2h command. when msb chip (chip #2) shows ready state, host can issue another opera- tion command to msb chip (chip #2). this interleaving algorithm improves t he system throughput almost twice. the host can issue page operation command to each chip individually. this reduces the time lag for the completion of operation. notes : during interleave operations, 70h command is prohibited. table . f1h/f2h read status register definition note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o no. page program block erase read definition i/o 0 chip pass/fail chip pass/fail not use pass : "0" fail : "1" i/o 1 plane0 pass/fail plane0 pass/fail not use pass : "0" fail : "1" i/o 2 plane1 pass/fail plane1 pass/fail not use pass : "0" fail : "1" i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy b usy : "0" ready : "1" i/o 7 write protect write protect write protect prote cted : "0" not protected : "1" www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 21 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d r/b (#1) busy of chip #1 i/o x 80h 10h f1h chip address : low add & data 80h 10h chip address : high add & data busy of chip #2 internal only internal only r/b interleaving page program ab c d another page program on chip #1 state a : chip #1 is executing page program operation and chip #2 is in r eady state. so the host can issue page program command to chip # 2. state b : both chip #1 and chip #2 are executing page program operation. state c : page program on chip #1 is terminated, but page program on chip #2 is still operating. and t he system should issue f1h comman d to detect the status of chip #1. if chip #1 is ready, status i/o6 is "1" and the system can issue another page program command to chip #1. state d : chip #1 and chip #2 are ready. according to the above process, the system can oper ate page program on chip #1 and chip #2 alternately. r/b (#2) i/o6 ready busy "1" "0" www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 22 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d add 00h 30h 00h 30h add 00h 05h chip address: low add f1h e0h data out add 00h 05h chip address: high col.add e0h data out f2h r/b (#1) i/o x internal only r/b (#2) internal only r/b interleaving page read operation chip address: low chip address: high add i/o6 ready busy "1" "0" column address i/o6 ready busy "1" "0" 1 1 r/b (#1) i/o x internal only r/b (#2) internal only r/b state a : chip #1 is executing page read operation, and chip #2 is in r eady state. so the host can issue page read command to chip #2. state b : both chip #1 and chip #2 are executing page read operation. state c : page read on chip #1 is completed and chip #2 is still executing page read operation. state d : data out of chip #1 and chip #2 is executing. state e : chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the data out command to chip #1. f2h command is required to check the status of chip #2 to issue the data out command to chip #2. according to the above process, the system can operate page read on chip #1 and chip #2 alternately. abc d e d www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 23 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d r/b (#1) busy of chip #1 i/o x 60h d0h f1h chip address : low add 60h d0h chip address : high add busy of chip #2 internal only r/b (#2) internal only interleaving block erase ab c d state a : chip #1 is executing block eras e operation, and chip #2 is in ready state. so t he host can issue block erase command to chip #2 . state b : both chip #1 and chip #2 are executing block erase operation. state c : block erase on chip #1 is term inated, but block erase on chip #2 is still oper ating. and the system should issue f1h command to detect the status of chip #1. if chip #1 is ready, status i/o6 is "1" and the system can issue another block erase command to chip #1. state d : chip #1 and chip #2 are ready. according to the above process, the system can oper ate block erase on chip #1 and chip #2 alternately. r/b another block erase on chip #1 i/o6 ready busy "1" "0" www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 24 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d r/b (#1) t dbsy i/o x f1h t prog of chip #1 internal only r/b (#2) internal only r/b 81h 10h plane address :high add & data 80h 11h plane address : low add & data 81h 10h plane address :high add & data 80h 11h plane address : low add & data t dbsy t prog of chip #2 r/b (#1) i/o x internal only r/b (#2) internal only r/b t prog of chip #2 1 1 interleaving two-plane page program state a : chip #1 is executing 2-plane page program operation, and chip #2 is in ready state. so the host can issue 2-plane page program command to chip #2. state b : both chip #1 and chip #2 are executing 2-plane page program operation. state c : 2-plane page program on chip #1 is completed and chip #1 is ready for the next operation. chip #2 is still executing 2-plane p age program operation. state d : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next page program command to chip #1. f2h command is required to check the status of chip #2 to issue the next page program command to chip #2. according to the above process, the system can operate tw o-plane page program on chip #1 and chip #2 alternately. ab cd chip address : low chip address :low chip address : high chip address :high another page program on chip #1 i/o6 ready busy "1" "0" www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 25 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d r/b (#1) i/o x f1h t bers of chip #1 internal only r/b (#2) internal only r/b 60h d0h add 60h plane address : low add 60h d0h add 60h add t bers of chip #2 t bers of chip #2 1 1 interleaving two-plane block erase r/b (#1) i/o x internal only r/b (#2) internal only r/b ab c state a : chip #1 is executing 2-plane block erase operat ion, and chip #2 is in ready state. so the host can issue 2-plane block erase co mmand to chip #2. state b : both chip #1 and chip #2 are exec uting 2-plane block erase operation. state c : 2-plane block erase on chip #1 is comple ted and chip #1 is ready for the next operati on. chip #2 is still executing 2-plane bl ock erase operation. state d : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next block erase command to chip #1. f2h command is required to check the st atus of chip #2 to issue the nex t block erase command to chip #2. according to the above process, the system can operate two-plane block erase on chip #1 and chip #2 alternately. d another block erase on chip #1 i/o6 ready busy "1" "0" chip address : low plane address : high chip address : low plane address : low chip address : high plane address : high chip address : high www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 26 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d r/b (#1) i/o x internal only r/b (#2) internal only r/b 1 1 interleaving read to page program operation r/b (#1) i/o x internal only r/b (#2) internal only r/b ab c state a : chip #1 is executing page program operation, and chip #2 is in ready state. so the host can issue read command to chip #2. state b : both chip #1 is executing page program oper ation and chip #2 is executing read operation. state c : read operation on chip #2 is completed and chip #2 is ready for the next operation. chip #1 is still executing page program op eration. state d : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next command to chip #1. f2h command is required to check t he status of chip #2 to issue the next command to chip #2. as the above process, the system can operate interleave read to page porgram on chip #1 and chip #2 alternatively. d 10h 80h chip address : low add data in t prog of chip #1 05h 00h chip address : high add data out t r of chip #2 t prog of chip #1 add e0h i/o6 ready busy "1" "0" 30h 00h add column address chip address : high f1h i/o6 ready busy "1" "0" f2h www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 27 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d r/b (#1) i/o x internal only r/b (#2) internal only r/b 1 interleaving copy-back program operation (1/2) r/b (#1) i/o x internal only r/b (#2) internal only r/b 1 b c 05h 00h add e0h add t prog of chip #1 a chip address : high column address 35h 00h chip address : low add i/o6 ready busy "1" "0" f1h 05h 00h add e0h add data out chip address : low column address t r of chip #1 10h 85h chip address : low add & data 35h 00h chip address : high add t r of chip #2 i/o6 ready busy "1" "0" f2h 2 www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 28 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d interleaving copy-back program operation (2/2) state a : chip #1 is executing copy-back program operation, and chip #2 is in ready state. so the host can issue read for copy-back comma nd to chip #2. state b : chip #1 is executing copy-back program operation and chip #2 is executing read for copy-back operation. state c : read for copy-back operation on chip #2 is completed and chip #2 is ready for the next operation. chip #1 is still executing c opy-back program operation. state d : both chip #1 and chip #2 are executing copy-back program operation. state e : chip #2 is still executing a copy- back program operation, and chip #1 is in ready for the next operation. state f : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next command to chip #1. f2h command is required to check t he status of chip #2 to issue the next command to chip #2. as the above process, the system can operate interleave copy-back program on chip #1 and chip #2 alternatively. r/b (#1) i/o x internal only r/b (#2) internal only r/b 2 10h 85h chip address : high add & data e t prog of chip #2 data out i/o6 ready busy "1" "0" f1h d f www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 29 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d r/b (#1) i/o x internal only r/b (#2) internal only r/b 60h chip address : low add 1 1 interleaving two-plane copy back program (1/2) r/b (#1) i/o x internal r/b (#2) internal r/b a plane address : low tprog of chip #1 only only 60h add 35h 00h add 05h add e0h data out 00h add 05h add e0h data out tdbsy 2 chip address : low plane address : high chip address : low plane address : low column address chip address : low plane address : high column address f1h i/o6 ready busy "1" "0" t r of chip #1 85h add & data 11h 81h add & data 10h chip address : low plane address : low chip address : low plane address : high 60h add 60h add 35h chip address : high plane address : low chip address : high plane address : high www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 30 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d r/b (#1) i/o x f1h internal r/b (#2) internal r/b 3 2 interleaving two-plane copy back program (2/2) r/b (#1) i/o x internal r/b (#2) internal r/b c d only only 00h add 05h add e0h data out 85h add & data 11h 81h add & data 10h only only tprog of chip #1 tprog of chip #2 3 e chip address : high plane address : high column address chip address : high plane address : low chip address : high plane address : high i/o6 ready busy "1" "0" 00h add 05h add e0h data out chip address : high plane address : low column address t r of chip #2 f2h i/o6 ready busy "1" "0" b state a : chip #1 is executing 2-plane copy -back program operation, and chip #2 is in ready state. so the host can issue 2-plane read for copy-back command to chip #2. state b : chip #1 is executing 2-plane copy-bac k program operation and chip #2 is exec uting 2-plane read for copy-back operation. state c : 2-plane read for copy-back operation on chip #2 is completed and chip #2 is ready for the next operation. chip #1 is still exe cuting 2-plane copy-back program operation. state d : both chip #1 and chip #2 are exec uting 2-plane copy-back program operation. state e : chip #2 is still executing a 2-plane copy-back program operation, and chip #1 is in ready for the next operation. state f : both chip #1 and chip #2 are ready. note : *f1h command is required to check the status of chip #1 to issue the next command to chip #1. f2h command is required to check the status of chip #2 to issue the next command to chip #2. as the above process, the system can operate interleave 2-pl ane copy-back program on chip #1 and chip #2 alternatively. tdbsy www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 31 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or seri al access as shown below. the internal 4,314byte data registers are utilized as separate buf fers for this operation and the system desig n gets more flexible. in addition, for v oice or audio applications whic h use slow cycle time on the order of -seconds, de-activating ce during the data-loading and serial access would provide significant sa vings in power consumption. figure 4. program operation with ce don?t-care. ce we t wp t ch t cs address(5cycles) 80h data input ce cle ale we data input ce don?t-care 10h address(5cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/b t r re t cea out t rea ce re i/o 0 ~ 7 figure 5. read operation with ce don?t-care. 30h i/ox i/ox www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 32 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d command latch cycle ce we cle ale command address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh note device i/o data address i/ox data in/out col. add1 col. add2 row add1 row add2 row add3 K9LBG08U0D i/o 0 ~ i/o 7 4,314byte a0~a7 a8~a12 a13~a20 a21~a28 a29~a32 i/ox ce we cle ale col. add1 t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t ds t dh t wp i/ox col. add2 row add1 row add2 t wc t wh t alh t als t ds t dh row add3 t alh t cls www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 33 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d input data latch cycle ce cle we din 0 din 1 din final ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp i/ox * serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t rhoh t rea t reh t rea t rhz i/ox t chz t rhz notes : 1.transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 2. trloh is valid when frequency is higher than 20mhz. trhoh starts to be valid when frequency is lower than 20mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 34 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d status read cycle ce we cle re 70h/f1h/f2h status output t clr t clh t wp t ch t ds t dh t rea t ir t rhoh t whr t cea t cls i/ox t chz t rhz t cs re ce r/b i/ox t rr t cea t rea t rp t reh t rc t rhz t chz serial access cycle after read (edo type, cle=l, we =h, ale=l) t rhoh t rloh dout dout t rea notes : 1. transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 2. trloh is valid when frequency is higher than 20mhz. trhoh starts to be valid when frequency is lower than 20mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 35 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc row add2 30h t clr i/ox i/ox col. add1 col. add2 row add1 row add2 row add3 row add3 t clr t csd www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 36 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t w b t ar t r t rr t r c 30h/35h 05h column address dout m dout m+1 i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add3 e0h t rhw t clr t whr t rea www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 37 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d cache read operation(1/2) ce cle r/b we ale re i/ox 1 tdcbsyr trc 31h twb trr d0 d1 page address m tdcbsyr dout 31h twb trr d0 page address m+1 twc twb tr 00h 30h col. add. 0 col. add. 0 col. add1 col. add2 row add1 row add2 row add3 notes : 1. the column address will be reset to 0 by the 31h command input . 2. cache read operation is available only within a block. www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 38 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d cache read operation(2/2) ce cle r/b we ale re i/ox tdcbsyr trc dout 31h twb trr d0 d1 page address m+2 col. add. 0 1 tdcbsyr trc dout 31h twb trr d0 d1 page address m+3 col. add. 0 tdcbsyr trc dout 3fh twb tdh d0 d1 page address m+4 col. add. 0 notes : 1. the column address will be reset to 0 by the 31h and 3fh command input . 2. cache read operation is available only within a block. www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 39 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d 00h column address tw row address twc column address 05h dout n 00h column address tw row address twc column address 05h e0h dout m 60h tw row address twc 60h tw row address twc 30h 1 1 ce cle r/b we ale re i/ox ce cle r/b we ale re i/ox busy t wb t r t rea t whr t clr t whr t clr t rea e0h t rc t rc dout n+1 t rhw dout m+1 two-plane page read operation with two-plane random data out page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n column address : fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address : valid column address : fixed ?low? page address page m plane address : fixed ?high? block address : block n column address : valid col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 col. add1 col. add2 row add1 row add2 row add3 row add1 row add2 row add3 row add1 row add2 row add3 col. add1 col. add2 chip address : chip a chip address : chip a chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 40 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d 00h column address tw row address twc column address 05h dout n 00h column address tw row address twc column address 05h e0h dout m 60h tw row address twc 60h tw row address twc 33h 1 1 ce cle r/b we ale re i/ox ce cle r/b we ale re i/ox busy t wb t r t rea t whr t clr t whr t clr t rea e0h t rc t rc dout n+1 dout m+1 two-plane cache read operation with two-plane random data out (1/2) page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n column address : fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address : valid column address : fixed ?low? page address page m plane address : fixed ?high? block address : block n column address : valid col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 col. add1 col. add2 row add1 row add2 row add3 row add1 row add2 row add3 row add1 row add2 row add3 col. add1 col. add2 31h tdcbsyr twb 2 max. 127 times repeatable chip address : chip a chip address : chip a chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 41 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d 00h column address tw row address twc column address 05h dout n 00h column address tw row address twc column address 05h e0h dout m 2 t rea t whr t clr t whr t clr t rea e0h t rc t rc dout n+1 dout m+1 column address : fixed ?low? page address : page m+n plane address : fixed ?low? block address : block n column address : valid column address : fixed ?low? page address page m+n plane address : fixed ?high? block address : block n column address : valid col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 two-plane cache read operation with two-plane random data out (2/2) ce cle r/b we ale re i/ox 3fh tdcbsyr twb notes : 1. the column address will be reset to 0 by the 3fh command input . 2. cache read operation is available only within a block. 3. make sure to terminate the operation with 3fh command. if the operation is terminated by 31h command, monitor i/o 6 (ready/ busy) by issuing status read command (70h) and make sure the previous page read operation is completed. if the page read operation is completed, issue ffh reset before n ext operation. chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 42 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d page program operation ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc i/ox co.l add1 col. add2 row add1 row add2 row add3 notes : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl t whr www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 43 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d page program operation with random data input ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc 85h random data input command column address t wc din j din k serial input i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add3 notes : 1. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl t adl t whr i/o 0 =0 successful program i/o 0 =1 error in program www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 44 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d 00h i/o x 85h column address row address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc busy t wb t r busy 10h copy-back data input command 35h column address row address data 1 data n col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add1 row add2 row add3 row add3 70h notes : 1. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t adl t whr data 1 data n t rc copy-back program operation with random data input ce cle r/b we ale re i/ox www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 45 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d cache program operation (available only within a block) ce cle r/b we ale re 80h din n din 15h m serial data input command column address serial input program max. 127 times repeatable tcbsy twb twc command last page input & program t cbsy : max. 3000us (dummy) din n din 10h tprog* 2 twb i/o 80h col. add1,2 & row add1,2, 3 r/b data address & data input 15h 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h ex.) cache program t cbsy t cbsy t cbsy t prog* 2 program confirm command (true) 80h 70h 70h m row address i/ox i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add1 row add2 row add3 row add3 tadl tadl notes : 1 . tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. 2 . since programming the last page does not employ caching, the program time has to be that of page program. however, if the previous program cycle with the cache data has not finished, the actual program cycle of the last pag e is initiated only after completion of the previous cycle, which can be expr essed as the fo llowing formula. tprog = program time for the last page + program time for the ( last -1) th page - (command input cycle time + address input cycle time + last page data loading time) www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 46 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d two-plane page program operation 80h i/o 0 ~ 7 r/b 11h ex.) two-plane page program t dbsy address & data input 81h 10h address & data input 70h t prog col. add1,2 & row add 1,2,3 4,314 byte data ce cle r/b we ale re 80h din n din 11h m serial data input command column address program tdbsy twb twc command (dummy) din n 10h i/o program confirm command (true) 81h 70h page row address i/ox 1 up to 4,314 byte serial input din m read status command t dbsy : typ. 500ns max. 1 s col. add1 col. add2 row add1 row add2 row add3 col. add1 col. add2 row add1 row add2 row add3 col. add1,2 & row add 1,2,3 4,314 byte data column address : valid page address : page m plane address : fixed ?low? block address : block n column address : valid page address : page m plane address : fixed ?high? block address : block n note: any command between 11h and 81h is prohibited except 70h/f1hf2h and ffh. note twhr i/o 0 =1 error in program i/o 0 =0 successful program twb tprog data chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 47 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d ce cle r/b we ale re i/ox tadl 80h din 0 din 1 11h tdbsy twb din 4313 1 81h din 0 din 1 15h tcbsy twb din 4313 80h tadl two-plane cache program operation twc twc col. add1 col. add2 row add1 row add2 row. add3 column address row address col. add1 program command (cache) ce cle r/b we ale re i/ox tadl 80h din 0 din 1 11h tdbsy twb din 4313 81h din 0 din 1 10h tprog* twb din 4313 tadl twc twc col. add1 col. add2 row add1 row add2 row add2 col. add1 col. add2 row add1 row add2 row. add3 column address row address column address row address 1 program confirm (true) command notes : 1 . tprog = program time for the last page + program time for the ( last -1) th page - (command input cycle time + address input cycle time + last page data loading time) 2 . make sure to terminate the operation with 80h-10h- command sequence. if the operation is terminated by 80h-15h command seque nce, monitor i/o 6 (ready/busy) by issuing status read command (70h) and make sure the previous page program operation is completed. if the p age program operation is completed issue ffh reset before next operation. col. add1 col. add2 row add1 row add2 row. add3 column address row address www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 48 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc auto block erase setup command i/ox row add1 row add2 row add3 t whr www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 49 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d two-plane block erase operation block erase setup command1 erase confirm command read status command 60h row add1,2,3 i/o 0 ~ 7 r/b 60h a 9 ~ a 25 d0h t bers ex.) address restriction for tw o-plane block erase operation ce cle r/b i/o x we ale re 60h row add1 d0h 70h i/o 0 busy t wb t bers t wc d0h 70h address address row add1,2,3 i/o 0 = 0 successful erase i/o 0 = 1 error in erase row add2 row add3 page address : fixed ?low? plane address : fixed ?low? block address : block n page address : fixed ?low? plane address : fixed ?high? block address : block n 60h row add1 d0h row add2 row add3 row address t wc block erase setup command2 row address t whr chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 50 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d read id operation ce cle we ale re 90h read id command maker code device code 00h ech t rea address 1cycle i/ox t ar device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle 6th cycle K9LBG08U0D d7h d5h 29h 38h 41h k9hcg08u1d same as K9LBG08U0D in it k9xdg08u5d device 4th cyc. code 3rd cyc. 5th cyc. 6th cyc. www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 51 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d id definition table 90 id : access command = 90h description 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte 6 th byte maker code device code internal chip number, cell type, number of simultaneously programmed pages, etc. page size, block size,redundant area size. plane number, ecc level, organization. device technology, edo, interface. 3rd id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not support support 0 1 cache program not support support 0 1 4th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 2kb 4kb 8kb reserved 0 0 0 1 1 0 1 1 block size (w/o redundant area ) 128kb 256kb 512kb 1mb reserved reserved reserved reserved 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 redundant area size ( byte / page size) reserved 128b 218b reserved reserved reserved reserved reserved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 52 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d 5th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 ecc level 1bit / 512b 2bit / 512b 4bit / 512b 8bit / 512b 16bit / 512b reserved reserved reserved 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 reserved 0 0 0 6th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 device version 50nm 40nm reserved reserved reserved reserved reserved reserved 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 0 edo not support support 0 1 interface sdr ddr 0 1 reserved 0 0 0 www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 53 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d device operation page read page read is initiated by writing 00h-30h to the command register along with five address cycles. after initial power up, 00h c ommand is latched. therefore only five address cycles and 30h command init iates that operation after initial power up. the 4,314 bytes of data within the selected page are transferred to the ca che registers via data registers in less than 60 s(t r ). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the cache registers, they may be read out in 30ns(k9xdg 08u5d: 50ns) cycle time by sequentially pulsing re . the repetitive high to low transi- tions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the co nsecutive sequential data by writing random data output command. the column address of next data, which is going to be out, ma y be changed to the address which follows random data output com- mand. random data output can be operated multiple time s regardless of how many times it is done in a page. figure 6. read operation address(5cycle) 00h col. add.1,2 & row add.1,2,3 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 54 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d figure 7. random data output in a page address 00h data output r/b re t r 30h/35h address 05h e0h 5cycles 2cycles data output data field spare field data field spare field i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 cache read cache read is an extension of page read, which is executed wi th 4,314byte data registers, and is available only within a block. since the device has 1 page of cache memory, serial data output ma y be executed while data in the memory cell is read into cach e registers. cache read is also initiated by writing 00h-30h to the command register along with five address cycles. after initial power up, 00h command is latched. therefore only five address cycles and 30h co mmand initiates that operation after initial power up. the 4,3 14 bytes of data within the selected page are transferred to the cache registers via data registers in less than 60 s(t r ). after issuing cache read command(31h), read data in the data registers is transfe rred to cache registers for a short period of time(tdcbsyr). while the data in the cache registers is read out in 30ns cycle time by sequentially pulsing re, data of next page is transferred to the data registers. by issuing last cache read command(3fh), last data is transferred to the cache registers from the data register s after the completion of transfer from memory cell to data r egisters. cache read is available only within a block. www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 55 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d figure 8. cache read ce cle r/b we ale re i/ox note -. if the 31h command is issued to the device, the data content of the next page is transferred to the data registers during se rial data out from the cache registers, and therefore the tr (data transfer from memory cell to data register) will be reduced. 1. normal read. data is transferred from page n to cache regist ers through data registers. during this time period, the device outputs busy state for tr max. 2. after the ready/busy returns to ready, 31h command is issued and data is transferred to cache registers from data registers again. this data transfer takes tdcbsyr max and the completion of this time period c an be detected by ready/busy signal. 3. data of page n+1 is transferred to data registers from cell while the data of page n in cache registers can be read out by r e clock simultaneously. 4. the 31h command makes data of page n+1 transfer to cache registers from data registers after the completion of the transfer from cell to data registers. the device outputs busy state for tdcbsyr max..this busy period depends on the combination of the internal data transfer time from cell to data registe rs and the serial data out time. 5. data of page n+2 is transferred to data registers from cell while the data of page n+1 in cache registers can be read out by re clock simultaneously. 6. the 3fh command makes the data of page n+2 transfer to the cache registers from the data registers after the completion of t ransfer form cell to data registers. the device outputs busy state for tdcbsyr max.this busy period depends on the combi nation of the internal data transfer time from cell to data re gisters and the transfer from data registers to cache registers. 7. data of page n+2 in cache registers can be read out, but si nce the 3fh command does not transfer the data from the memory c ell to data registers, the device can accept new command input immediately after the completion of serial data out. the device has a read operation with cache registers that enabl es the high speed read operation shown below. when the block add ress changes, this sequence has to be started from the beginning. 00h 30h 31h 31h 3fh 0 1 2 3 4313 0 1 2 3 4313 0 1 2 3 4313 30h 31h & re clock page n 31h & re clock page n+1 3fh & re clock page n+2 page n page n+1 page n+2 tr page row column address address column 0 page address n page address n+1 page address n+2 page n page n+1 page n+2 1 1 12 2 2 3 4 4 35 6 7 5 5 6 7 tdcbsyr tdcbsyr tdcbsyr cache register data register www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 56 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d two-plane page read two-plane page read is an extension of page read, for a single pl ane with 4,314 byte data registers. since the device is equipp ed with two memory planes, activating the two sets of 4,314 by te data registers enables a random read of two pages. two-plane page read is initiated by repeating command 60 h followed by three address cycles twice. in this case, only same page of same block can be selected from each plane. after read confirm command(30h) the 8,628 bytes of data within the selected two page are transferred to the cache registers via data registers in less than 60us(tr). the system controller can detect the completion of data transfer(tr) by monitoring the ou tput of r/b pin. once the data is loaded into the cache registers, the data output of first plane can be read out by issuing command 00h with fi ve address cycles, command 05h with two column address and finally e0h. the data output of second plane can be read out using the identical command sequences. figure 9. two-plane page read operation with two-plane random data out 60h i/o x r/b 60h 30h t r address (3 cycle) address (3 cycle) page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address : valid 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?high? block address : block n column address : valid chip address : chip a chip address : chip a chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 57 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d two-plane cache read two-plane cache read is an extension of cache read, for a si ngle plane with 4,314 byte data registers. since the device is equipped with two memory planes, activating the two sets of 4, 314 byte data registers enables a cache read of two pages. two- plane cache read is initiated by repeating command 60h followed by three address cycles twice. in this case only same page of same block can be selected from each plane. after read confirm command(33h) the 8,628 bytes of data within t he selected two page are transferred to the cache registers via data registers in less than 60us(tr). after issuing cache r ead command(31h), read data in the data registers is transferred to cache registers for a short period of time(tdcbsyr). once the data is loaded into the cache registers from data registers, the data o utput of first plane can be read out by issuing co mmand 00h with five address cycles, command 05h with two column address and finally e0h. the data output of second plane can be read out using t he identical command sequences. the detail sequence of two-plane cache read is shown in figure 10. figure 10. two-plane cache read operation with two-plane random data out 60h i/o x r/b 60h 33h t r address (3 cycle) address (3 cycle) page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address : valid 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m plane address : fixed ?high? block address : block n column address : valid 31h t dcbsyr r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 3 col. add. 1,2 & row add.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m+n plane address : fixed ?low? block address : block n column address : valid 4 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 4 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 column address : fixed ?low? page address : page m+n plane address : fixed ?high? block address : block n column address : valid 3fh 3 t dcbsyr chip address : chip a chip address : chip a chip address : chip a chip address : chip a chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 58 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d figure 11. program & read status operation 80h r/b address & data input i/o0 pass data 10h 70h fail t prog i/ox col. add.1,2 & row add.1,2,3 "0" "1" page program the device is programmed basical ly on a page basis, and the number of consecutiv e partial page programming operation within the same page without an intervening erase operation must not exceed 1 time for the page. the addressing should be done in sequenti al order in a block. a page program cycle consists of a serial data loading period in which up to 4,314bytes of data may be loaded into the data registers via cache registers, followed by a non-vola tile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input command(80h) , followed by the fi ve cycle address input s and then serial data loading. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address for the next data, which wi ll be entered, may be changed to the address which follows rando m data input command(85h). random data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming process. writing 10h alone wit hout previously entering the serial data will not initiate the programming process. the internal write state controller automat ically executes the algorithm s and tim- ings necessary for program and verify, thereb y freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status r egister. the system controller can detect the completion of a p ro- gram cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the p age program is complete, the write status bit(i/o 0) may be checked. the internal write verify detect s only errors for "1"s that are not succes sfully programmed to "0"s. the command regis ter remains in read status command mode until another va lid command is written to the command register. figure 12. random data input in a page 80h r/b address & data input i/o0 pass 10h 70h fail t prog 85h address & data input i/ox col. add.1,2 & row add1,2,3 col. add.1,2 data data "0" "1" www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 59 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d copy-back program note : 1. copy-back program operation is allowed only within the same memory plane. copy-back program with read for copy-back is configured to quickly and efficiently rewrite data stored in one page without data re- loading when the bit error is not in data stored. since the time-consuming re-loading cycles ar e removed, the system performanc e is improved. the benefit is especially obvious when a portion of a bl ock is updated and the rest of the block also needs to be cop ied to the newly assigned free block. copy-back oper ation is a sequential execution of read fo r copy-back and of copy-back program wit h the destination page address. a read operation with "35h" command and the address of the source page moves the whole 4,314-byte data into the internal data buffer. a bit error is checked by sequential reading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore copy-back program oper ation is initiated by issuing page-copy data-input command (85h) with destination page address. actual programming operati on begins after program confirm command (10h) is issued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system contr ol- ler can detect the completion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. when the copy-back program is complete, the write status bit(i/o 0) may be checked(figure 13 & figure 14). the command register remains in read status command mode until another valid command is written to the command register. during copy-back program, data modification is possible us ing random data input command (85h) as shown in figure14. "0" "1" figure 13. page copy-back program operation 00h r/b add.(5cycles) i/o0 pass fail t prog t r source address destination address i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 35h data output 85h add.(5cycles) 10h 70h figure 14. page copy-back program operation with random data input r/b source address destination address there is no limitation for the number of repetition. i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 col. add.1,2 00h add.(5cycles) 35h t r data output 85h add.(5cycles) data 85h add.(2cycles) data 10h t prog 70h www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 60 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d cache program cache program is an extension of page pr ogram, which is executed with 4314byte data r egisters, and is available only within a b lock. since the device has 1 page of cache memory, serial data input may be executed while data stored in data registers are programm ed into memory cell. after writing the first set of data up to 4314byte into the selected cache registers, cache program command (15h) instead of ac tual page program (10h) is inputted to make cache registers free and to start internal program operation. to transfer data from cach e reg- isters to data registers, the device remains in busy state fo r a short period of time(tcbsy) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. read status command (70h) may be issued to find out when cache registers be come ready by polling the cache-busy status bit(i/o 6). pass/fail status of only t he pre- vious page is available upon the return to ready state. when t he next set of data is inputted with the cache program command, tcbsy is affected by the progress of pending internal programming. the programming of the cache registers is initiated only whe n the pending program cycle is finished and the data registers are av ailable for the transfer of data from cache registers. the s tatus bit(i/o5) for internal ready/busy may be poll ed to identify the completion of internal programming. if the system monitors the progress of programming only with r/b , the last page of the target programming sequence must be programmed with actual page program command (10h). figure 15. cache program(1/2) 80h r/b 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h t cbsy t cbsy t cbsy t prog* 2 70h address & data input* 15h col. add1,2 & row add1,2,3 col. add1,2 & row add1,2,3 col. add1,2 & row add1,2,3 data data data col. add1,2 & row add1,2,3 data i/ox notes : 1. cache read operation is available only within a block. 2. since programming the last page does not employ caching, the program time has to be that of page program. howev er, if the previous program cycle with the cache data has not finished, the ac tual program cycle of the last pag e is initiated only after completion of t he previous cycle, which can be expr essed as the following formula. tprog = program time for the last page + program time for the ( last -1) th page - (program command cycle time + last page data loading time) www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 61 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d figure 15. cache program(2/2) 15h page k cache register data register ce cle r/b we ale re 80h din n din 15h m max. 127 times repeatable last page input & program din n din 10h i/o 80h 70h m i/ox page k page k page k+1 page k page k page k+1 page k+1 page k 1 1 2 2 3 3 4 3 4 4 10h note - issuing the 15h command to the device after serial data i nput initiates the program operation with cache registers. 1. data for page k is input to cache registers. 2. data is transferred to the data registers by the 15h command. during the transfer the ready/busy outputs busy state (tcbsy). 3. data for page k+1 is input to cache register s while the data of the page k is being programmed. 4. the programming with cache registers is terminated by the 10h command . when the device becomes ready, it shows that the int ernal programming of the page k+1 is completed. tprog* = program time for the last page + program time for the ( last -1) th page - (command input cycle time + address input cycle time + last page data loading time) tcbsy tprog* www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 62 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d pass/fail status for each page programmed by the cache pr ogram operation can be detected by the read status operation. ? i/o 0 : pass/fail of the current page program operation. ? i/o 1 : pass/fail of the previous page program operation. the pass/fail status on i/o 0 and i/o 1 are valid under the following conditions. ? status on i/o 0 : true ready/busy is ready state. the true ready/busy is output on i/o 5 by read status operation or r/b pin after the 10h command. ? status on i/o 1 :cache read/busy is ready state. the cache ready/busy is output on i/o 6 by read status operation or r/b pin after the 15h command. example) 70h 80h....15h status out 80h....15h 70h status out 70h status out 80h....15h i/o1 => invalid page1 page1 page n-2 invalid page n-1 70h status out 80h....10h 70h status out 70h status out i/o0 => invalid invalid page2 invalid invalid page n page 1 page 2 page n-1 page n r/b pin cache true page 1 page 2 page n-1 page n ready/busy ready/busy during both true ready/busy and cache ready/busy return to ready state, the pass/fail for previous page and current page can be shown through i/o 1 and i/o 0 concurrently. www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 63 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d two-plane page program two-plane page program is an extension of page program, for a si ngle plane with 4,314 byte data registers. since the device is equipped with two memory planes, activating the two sets of 4,314 byte data registers enables a simultaneous programming of two pages. after writing the first set of data up to 4,314 byte into the se lected data registers via cache registers, dummy page program c om- mand (11h) instead of actual page program command (10h) is i nputted to finish data-loading of the first plane. since no program - ming process is involved, r/b remains in busy state for a short period of ti me(tdbsy). read status command (70h) may be issued to find out when the device returns to ready state by polling t he ready/busy status bit(i/o 6). then the next set of data for t he other plane is inputted after the 81h command and address sequences. after inputting data for the last plane, actual true page pro- gram(10h) instead of dummy page program command (11h) must be followed to start the programming process. the operation of r/ b and read status is the same as that of page program. althou gh two planes are programmed simult aneously, pass/fail is not avail - able for each page when the program operation completes. status bit of i/o 0 is set to "1" when any of the pages fails. restriction in addressing with two-pl ane page program is shown is figure16. figure 16. two-plane page program 80h 11h data input plane 0 (2048 block) block 0 block 2 block 4094 block 4092 note :1. it is noticeable that same row address except for a 20 is applied to the two blocks 81h 10h plane 1 (2048 block) block 1 block 3 block 4095 block 4093 column address : valid page address : page m plane address : fixed ?low? block address : block n column address : valid page address : page m plane address : fixed ?high? block address : block n 2. any command between 11h and 81h is prohibited except 70h/f1h/f2h and ffh. note* 2 80h i/o 0 ~ 7 r/b address & data input 11h 81h 10h t dbsy t prog address & data input pass 70h i/o0 fail "0" "1" chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 64 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d figure 17. two-plane copy-back program operation r/b 85h 70h t prog add.(5cycles) destination address 10h i/ox col. add.1,2 & row add.1,2,3 81h add.(5cycles) destination address col. add.1,2 & row add.1,2,3 11h t dbsy two-plane copy-back program two-plane copy-back program is an extension of copy-back program, for a single plane with 4314 byte data registers. since the device is equipped with two memory pl anes, activating the two sets of 4314 byte data registers enables a simultaneous programming of two pages. 3 note2 60h i/o x r/b 60h 35h t r address (3 cycle) address (3 cycle) 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 3 page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n column address: fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address: valid column address: fixed ?low? page address : page m plane address : fixed ?high? block address : block n column address: valid column address: fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address: fixed ?low? page address : page m plane address : fixed ?high? block address : block n chip address : chip a chip address : chip a chip address : chip a chip address : chip a chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 65 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d data field spare field (1) (3) plane0 source page target page (1) : two-plane read for copy back (2) : two-plane random data out (3) : two-plane copy-back program note : 1. copy-back program operation is allo wed only within the same memory plane. 2 . any command between 11h and 81h is prohibited except 70h/f1h/f2h and ffh. (2) data field spare field (1) (3) plane1 source page target page (2) www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 66 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d r/b 85h 11h t dbsy add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) r/b 81h 10h t prog add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) 3 4 4 destination address destination address figure 18. two-plane copy-back program operation with random data input note : 1. copy-back program operation is allo wed only within the same memory plane. 2 . any command between 11h and 81h is prohibited except 70h/f1h/f2h and ffh. note2 60h i/o x r/b 60h 35h t r address (3 cycle) address (3 cycle) 1 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 1 row add.1,2,3 row add.1,2,3 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 2 r/b data output i/ox 00h 05h address (5 cycle) e0h address (2 cycle) 2 col. add. 1,2 & row ad d.1,2,3 col. add.1,2 3 page address : page m plane address : fixed ?low? block address : block n page address : page m plane address : fixed ?high? block address : block n column address: fixed ?low? page address : page m plane address : fixed ?low? block address : block n column address: valid column address: valid column address: fixed ?low? page address : page m plane address : fixed ?high? block address : block n column address: valid page address : page m plane address : fixed ?low? block address : block n column address: valid column address: valid page address : page m plane address : fixed ?high? block address : block n column address: valid chip address : chip a chip address : chip a chip address : chip a chip address : chip a chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 67 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d two-plane cache program two-plane cache program is an extension of cache program, for a si ngle plane with 4,314 byte data r egisters. since the device i s equipped with two memory planes, activating the two sets of 4,314 byte data registers enables a simultaneous programming of two pages. figure 19. two-plane cache program operation i/o x r/b 1 r/b i/ox 1 column address : valid page address : page m plane address : fixed ?low? block address : block n column address : valid page address : page m plane address : fixed ?high? block address : block n 80h address & data input 11h 81h 15h address & data input column address : valid page address : page m+n plane address : fixed ?low? block address : block n column address : valid page address : page m+n plane address : fixed ?high? block address : block n 80h address & data input 11h 81h 10h address & data input t dbsy t dbsy t prog* 3 t cbsy note* 2 note : 1 . it is noticeable that same row address except for a 20 is applied to the two blocks 2 . any command between 11h and 81h is prohibited except 70h/f1h/f2h and ffh. 3 . since programming the last page does not employ caching, the program time has to be that of page program. however, if the previous program cycle with the ca che data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. tprog = program time for the last page + program time for the ( last -1) th page - (program command cycle time + last page data loading time) 80h 11h cache register plane 0 (2048 block) block 0 block 2 block 4094 block 4092 81h 15h plane 1 (2048 block) block 1 block 3 block 4095 block 4093 data register 1 2 3 1 2 3 3 chip address : chip a chip address : chip a chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 68 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d figure 21. two-plane block erase operation 60h i/o x r/b 60h d0h i/o0 pass fail t bers address (3 cycle) address (3 cycle) 70h "0" "1" page address : fixed ?low? plane address : fixed ?low? block address : block n page address : fixed ?low? plane address : fixed ?high? block address : block n two-plane block erase basic concept of two-plane block erase operat ion is identical to that of two-plane p age program. up to two blocks, one from eac h plane can be simultaneously erased. standard block erase comma nd sequences (block erase setup command(60h) followed by three address cycles) may be repeated up to twice for erasing up to two blocks. only one block should be selected from each pla ne. the erase confirm command(d0h) initiates the actual erasing process. the completion is detected by monitoring r/b pin or ready/ busy status bit (i/o 6). row add 1,2,3 row add 1,2,3 figure 20. block erase operation block erase the erase operation is done on a block basis. bl ock address loading is accomplished in thr ee cycles initiated by an erase setup command(60h). only plane address and block address are valid wh ile page address is ignored. t he erase confirm command(d0h) following the block address loading initiate s the internal erasing process. this tw o-step sequence of setup followed by executi on command ensures that memory contents are not a ccidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bi t(i/o 0) may be checked. figure 20 details the sequence. 60h row add 1,2,3 r/b address input(3cycle) i/o0 pass d0h 70h t bers i/ox "0" "1" chip address : chip a chip address : chip a www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 69 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d read status table 2. status register definition for 70h command note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. 2. n : current page, n-1: previous page. i/o page program block erase cache program read cache read definition i/o 0 pass/fail pass/fail pass/fail(n) not use not use pass : "0" fail : "1" i/o 1 not use not use pass/fail(n-1) not use not use pass : "0" fail : "1" i/o 2 not use not use not use n ot use not use don?t -cared i/o 3 not use not use not use n ot use not use don?t -cared i/o 4 not use not use not use n ot use not use don?t -cared i/o 5 not use not use true ready/busy not use true ready/busy busy : "0" ready : "1" i/o 6 ready/busy ready/busy cache ready/bus y ready/busy cache ready/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect write protect write protect protected : "0" not protected : "1" the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. afte r writing 70h or f1h/f2h command to the command register, a read cycle outputs the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for specific 70h status regist er definitions and table 3 for specific f1h status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, the read command(00h) should be given before starting rea d cycles. table 3. f1h/f2h read status register definition note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o no. page program block erase read definition i/o 0 chip pass/fail chip pass/fail not use pass : "0" fail : "1" i/o 1 plane0 pass/fail plane0 pass/fail not use pass : "0" fail : "1" i/o 2 plane1 pass/fail plane1 pass/fail not use pass : "0" fail : "1" i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy b usy : "0" ready : "1" i/o 7 write protect write protect write protect prote cted : "0" not protected : "1" www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 70 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d figure 22. read id operation ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea read id the device contains a product identification mode, initiated by wr iting 90h to the command register, followed by an address inp ut of 00h. six read cycles sequentially output the manufacturer code(ech), the device code, 3r d, 4th, 5th and 6th cycle id respective ly. the command register remains in read id mode until further commands are issued to it. figure 22 shows the operation sequence. figure 23. reset operation reset the device offers a reset feature, executed by writing ffh to t he command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 4 for device st atus after reset operation. if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin changes to low for trst after the reset command is written. refer to figure 23 below. ffh i/o x r/b t rst t whr t clr device 4th cyc. code ech 3rd cyc. 5th cyc. table 4. device status after power-up after reset operation mode 00h command is latched waiting for next command 6th cyc. device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle 6th cycle K9LBG08U0D d7h d5h 29h 38h 41h k9hcg08u1d same as K9LBG08U0D in it k9xdg08u5d www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 71 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d table 5 . paired page address information paired page address paired page address 00h 04h 01h 05h 02h 08h 03h 09h 06h 0ch 07h 0dh 0ah 10h 0bh 11h 0eh 14h 0fh 15h 12h 18h 13h 19h 16h 1ch 17h 1dh 1ah 20h 1bh 21h 1eh 24h 1fh 25h 22h 28h 23h 29h 26h 2ch 27h 2dh 2ah 30h 2bh 31h 2eh 34h 2fh 35h 32h 38h 33h 39h 36h 3ch 37h 3dh 3ah 40h 3bh 41h 3eh 44h 3fh 45h 42h 48h 43h 49h 46h 4ch 47h 4dh 4ah 50h 4bh 51h 4eh 54h 4fh 55h 52h 58h 53h 59h 56h 5ch 57h 5dh 5ah 60h 5bh 61h 5eh 64h 5fh 65h 62h 68h 63h 69h 66h 6ch 67h 6dh 6ah 70h 6bh 71h 6eh 74h 6fh 75h 72h 78h 73h 79h 76h 7ch 77h 7dh 7ah 7eh 7bh 7fh note: when program operation is abnormally aborted (ex. power-down, reset), not only page data under program but also paired page data may be damaged(table 5). www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 72 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d ready/busy the device has a r/b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/b pin is normally high but transitions to low after pr ogram or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal contro ller has finished the operation . the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obt ained with the following reference chart(fig.24). its value can be determined by the following guidance. v cc r/b open drain output device gnd rp ibusy c l busy ready vcc voh tf tr vol 3.3v device - v ol : 0.4v, v oh : 2.4v figure 24. rp vs tr ,tf & rp vs ibusy tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 c , c l = 50pf 1k 2k 3k 4k 100n 200n 2m 1m 50 tf 100 150 200 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maxi mum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + i l = 3.2v 8ma + i l www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 73 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d data protection & power up sequence the device internal initialization starts after the power suppl y reaches an appropriate level in the power on sequence. during the ini- tialization the device ready/busy signal indicates the busy state as shown in th e figure 25. in this time period, the acceptabl e com- mand is 70h(f1h/f2h). the device is designed to offer protection from any involuntar y program/erase during power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 2v(3.3v device). wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. the two step command s equence for program/erase provides additional software protection. figure 25. ac waveforms for power transition v cc wp high we ready/busy 5 ms max operation note :during the initialization, the device consumes a maximum current of 30ma (i cc 1) 100 s ~ 2.3v ~ 2.3v invalid don?t care don?t care www.datasheet.co.kr datasheet pdf - http://www..net/
flash memory 74 K9LBG08U0D k9hcg08u1d preliminary samsung confidential k9mdg08u5d k9pdg08u5d wp ac timing guide enabling wp during erase and program busy is prohibited. the eras e and program operations are enabled and disabled as follows: figure b-1. program operation 1. enable mode 80h 10h we i/o wp r/b tww(min.100ns) 2. disable mode 80h 10h tww(min.100ns) 1. enable mode 60h d0h tww(min.100ns) 2. disable mode 60h d0h tww(min.100ns) figure b-2. erase operation we i/o wp r/b we i/o wp r/b we i/o wp r/b www.datasheet.co.kr datasheet pdf - http://www..net/

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